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features ? six high-side and six low-side drivers ? outputs freely configurable as switch, half bridge, or h-bridge ? capable to switch all kinds of loads such as dc motors, bulbs, re sistors, capacitors and inductors ? 0.6a continuous current per switch ? low-side: r dson < 1.5 versus total temperature range ? high-side: r dson < 2.0 versus total temperature range ? very low quiescent current i s < 20 a in standby mode ? outputs short-circuit protected ? overtemperature prewarning and protection ? under- and overvoltage protection ? various diagnosis functions such as shor ted output, open load, overtemperature and power supply fail ? serial data interface ? daisy chaining possible ? so28 power package 1. description the u6815bm is a fully protected driver interface designed in 0.8-m bcdmos tech- nology. it is used to control up to 12 different loads by a microcontroller in automotive and industrial applications. each of the 6 high-side and 6 low-side drivers is capable of driving currents up to 600 ma. the drivers are freely configurable and can be controlled separately from a standard serial data interface. therefore, al l kinds of loads such as bulbs, resistors, capacitors, and inductors can be combined. the ic design especially supports the applications of h-brid ges to drive dc motors. protection is guaranteed for short-circuit conditions, overtemperature, under- and overvoltage. various diagnostic functions and a very low quiescent current in standby mode enable a wide range of applications. the u6815bm has automotive qualification for conducted interferences, emc protection, and 2-kv esd protection. dual hex dmos output driver with serial input control u6815bm 4545d?bcd?04/09
2 4545d?bcd?04/09 u6815bm figure 1-1. block diagram do inh power on re s et control logic f au lt detector s i h s 5 l s 5 h s 4 l s 4 h s 6 l s 6 h s 2 l s 2 h s 1 l s 1 input re g i s ter ouput re g i s ter h s 3 ov - protection v s l s 3 s r r o l d h s 1 l s 1 h s 2 l s 2 h s 3 l s 3 h s 4 l s 4 h s 5 l s 5 h s 6 l s 6 p s f t p i n h s c d s c t v cc f au lt detector f au lt detector f au lt detector f au lt detector f au lt detector f au lt detector f au lt detector f au lt detector vcc v s 15 26 25 di clk c s 1 8 17 24 1 3 12 3 22 8 16 14 11 4 1 27 10 5 h s 1h s 2h s3 h s 4h s 5h s 6 l s 1l s 2l s3 l s 4l s 5l s 6 v s v s gnd gnd gnd gnd gnd gnd gnd gnd vcc f au lt detector o s c uv - protection therm a l protection f au lt detector f au lt detector 6 7 8 9 20 21 22 2 3 19
3 4545d?bcd?04/09 u6815bm 2. pin configuration figure 2-1. pinning so28 24 3 6 5 8 710 914 1 3 12 11 h s 5 l s 5l s 4 h s 4 gnd v s gnd u6 8 15bm gnd v s gnd l s 2 h s 2 h s3 l s3 l s 6 h s 6 clk di gnd c s le a d fr a me gnd gnd vcc gnd h s 1 l s 1 inh do 27 2 8 25 26 2 3 24 21 22 19 20 15 16 17 1 8 1 table 2-1. pin description pin symbol function 1ls5 low-side driver output 5, power-mo s open drain with internal reverse diode, ov ervoltage protection by active zenering, short-circuit protection, diagnosis for short and open load 2hs5 high-side driver output 5, power-mos open drain wit h internal reverse diode, overvoltage protection by active zenering, short-circuit protection, diagnosis for short and open load 3 hs4 high-side driver output 4 (see pin 2) 4 ls4 low-side driver output 4 (see pin 1) 5 vs power supply output stages hs4, hs5, hs6, inte rnal supply; external connection to pin 10 necessary 6, 7, 8, 9 gnd ground, reference potential, intern al connection to pin 20 to 23, cooling tab 10 vs power supply output stages hs1, hs2 and hs3 11 ls3 low-side driver output 3 (see pin 1) 12 hs3 high-side driver output 3 (see pin 2) 13 hs2 high-side driver output 2 (see pin 2) 14 ls2 low-side driver output 2 (see pin 1) 15 hs1 high-side driver output 1 (see pin 2) 16 ls1 low-side driver output 1 (see pin 1) 17 inh inhibit input, 5-v logic input with internal pull down, low = standby, high = normal operating 18 do serial data output, 5-v cmos logic level tristate output for output (status) register data, sends 16-bit status information to the microcont roller (lsb is transferred first). output will remain tristated unless device is selected by cs = low, therefore, several ics can operate on one data output line only. 19 vcc logic supply voltage (5v) 20, 21, 22, 23 gnd ground (see pins 6 to 9) 24 cs chip select input, 5-v cmos logic level input wit h internal pull-up, low = serial communication is enabled, high = disabled 25 clk serial clock input, 5-v cmos logic level input with internal pull-down, controls serial data input interface and internal shift register (f max = 2 mhz) 26 di serial data input, 5-v cmos logic level input with in ternal pull-down, receives serial data from the control device, di expects a 16-bit control word with lsb being transferred first 27 ls6 low-side driver output 6 (see pin 1) 28 hs6 high-side driver output 6 (see pin 2)
4 4545d?bcd?04/09 u6815bm 3. functional description 3.1 serial interface data transfer starts with the falling edge of th e cs signal. data must appear at di synchronized to clk and is accepted on the falling edge of the clk signal. ls b (bit 0, srr) must be trans- ferred first. execution of new input data is enab led on the rising edge of the cs signal. when cs is high, pin do is in tristate condition. this output is enabled on the falling edge of cs. output data will change their state with th e rising edge of clk and stay st able until the next rising edge of clk appears. lsb (bit 0, tp) is transferred first. figure 3-1. data transfer 012 3 4567 8 91011121 3 14 15 s rr l s 1h s 1l s 2h s 2l s3 h s3 l s 4h s 4l s 5h s 5l s 6h s 6 old s ct s i tp s l s 1 s h s 1 s l s 2 s h s 2 s l s3 s h s3 s l s 4 s h s 4 s l s 5 s h s 5 s l s 6 s h s 6 s cd inh p s f do clk di c s table 3-1. input data protocol bit input register function 0srr status register reset (high = reset; the bits ps f, scd and overtemperature shutdown in the output data register are set to low) 1 ls1 controls output ls1 (h igh = switch output ls1 on) 2 hs1 controls output hs1 (high = switch output hs1 on) 3 ls2 see ls1 4 hs2 see hs1 5 ls3 see ls1 6 hs3 see hs1 7 ls4 see ls1 8 hs4 see hs1 9 ls5 see ls1 10 hs5 see hs1 11 ls6 see ls1 12 hs6 see hs1 13 old open-load detection (low = on) 14 sct programmable time delay for short circuit and overvoltage shutdown (short-circuit shutdown delay high/low = 100 ms/12.5 ms, overvoltage sh utdown delay high/low = 15 ms/3.5 ms 15 si software inhibit; low = standby, high = normal operation (data transfer is not affected by standby func tion because the digital part is still powered)
5 4545d?bcd?04/09 u6815bm after power-on reset, the input register has the following status: note: 1. bit 0 to 15 = high: overtemperature shutdown bit 15 (si) bit 14 (sct) bit 13 (old) bit 12 (hs6) bit 11 (ls6) bit 10 (hs5) bit 9 (ls5) bit 8 (hs4) bit 7 (ls4) bit 6 (hs3) bit 5 (ls3) bit 4 (hs2) bit 3 (ls2) bit 2 (hs1) bit 1 (ls1) bit 0 (srr) hhhlllllllllllll table 3-2. output data protocol bit output (status) register function 0 tp temperature prewarning: high = warning (overtemperature shut down) (1) 1 status ls1 normal operation: high = output is on, low = output is off open-load detection: high = open load, low = no ope n load (correct load condition is detected if the corresponding output is switched off) 2 status hs1 normal operation: high = output is on, low = output is off open-load detection: high = open load, low = no ope n load (correct load condition is detected if the corresponding output is switched off) 3 status ls2 description see ls1 4 status hs2 description see hs1 5 status ls3 description see ls1 6 status hs3 description see hs1 7 status ls4 description see ls1 8 status hs4 description see hs1 9 status ls5 description see ls1 10 status hs5 description see hs1 11 status ls6 description see ls1 12 status hs6 description see hs1 13 scd short circuit detected: set high, when at least one output is switched off by a short-circuit condition 14 inh inhibit: this bit is controlled by software (bit si in input register) and hardware inhibit (pin 17). high = standby, low = normal operation 15 psf power supply fail: over- or undervoltage at pin vs detected
6 4545d?bcd?04/09 u6815bm 4. power supply fail in the event of over or undervoltage at pin vs, an internal timer is started. when the overvoltage delay time (t dov ) programmed by the sct bit or the undervoltage delay time (t duv ) is reached, the power-supply fail bit (psf) in the output regi ster is set and all outputs are disabled. when normal voltage is present again, the outputs are immediately enabled. the psf bit remains high until it is reset by the srr bit in the input register. 5. open-load detection if the open-load detection bit (old) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current i hs1-6 , i ls1-6 ). if v vs ? v hs1-6 or v ls1-6 is lower than the open-load detection threshold (open-load condi- tion), the corresponding bit of the output in the output register is set to high. switching on an output stage with old bit set to low disables the open-load function for this output. 6. overtemperature protection if the junction temperature exceeds the thermal prewarning threshold, t jpw set , the temperature prewarning bit (tp) in the output register is set. when temperature falls below the thermal pre- warning threshold t jpw reset , the bit tp is reset. the tp bit can be read without transferring a complete 16-bit data word: with cs = high to low, the state of tp appears at pin do. after the microcontroller has read this information, cs is set high and the data transfer is interrupted with- out affecting the state of input and output registers. if the junction temperature exceeds the thermal shutdown threshold t j switch off , the outputs are disabled and all bits in the output register are set high. the outputs can be enabled again when the temperature falls below the thermal shutdown threshold, t j switch on , and when a high has been written to the srr bit in the input register. thermal prewarning and shutdown threshold have hysteresis. 7. short-circuit protection the output currents are limited by a current regulator. current limitation takes place when the over-current limitation and shutdown threshold (i hs1-6 , i ls1-6 ) are reached. simultaneously, an internal timer is started. the shorted output is disabled during a permanent short when the delay time (t dsd ) programmed by the short-circuit timer (sct) bit is reached. additionally, the short-circuit detection (scd) bit is set. if the temperature prewarning bit tp in the output regis- ter is set during a short, the shorted output is disabled immediately and scd bit is set. by writing a high to the srr bit in the input register, the scd bit is reset and the disabled outputs are enabled. 7.1 inhibit there are two ways to disable the u6815bm: 1. set bit si in the input register to zero 2. switch pin 17 (inh) to 0v in both cases, all output stages are turned off but the serial interface stays active. the output stages can be activated again by bit si = 1 or by pin 17 (inh) switched back to 5v.
7 4545d?bcd?04/09 u6815bm 8. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . all values refer to gnd pins. parameters pins symbol value unit supply voltage 5, 10 v vs ?0.3 to +40 v supply voltage, t < 0.5s; i s > ?2a 5, 10 v vs ?1 v supply voltage difference |v s_pin5 ? v s_pin10 | v vs 150 mv supply current 5, 10 i vs 1.4 a supply current, t < 200 ms 5, 10 i vs 2.6 a logic supply voltage 19 v vcc ?0.3 to +7 v input voltage 17 v inh ?0.3 to +17 v logic input voltage 24 to 26 v di, v clk, v cs ?0.3 to v vcc + 0.3 v logic output voltage 18 v do ?0.3 to v vcc + 0.3 v input current 17, 24 to 26 i inh, i di, i clk, i cs ?10 to +10 ma output current 18 i do ?10 to +10 ma output current 1 to 4, 11 to 16 i ls1 to i ls6 internally limited (see output specification) ma 27, 28 i hs1 to i hs6 ma output voltage 2, 3, 12, 13, 15, 28 hs1 to hs6 ?0.3 to +40 v 1, 4, 11, 14, 16, 27 ls1 to ls6 reverse conducting current (t pulse = 150 s) 2, 3, 12, 13, 15, 28 towards 5, 10 i hs1 to i hs6 17 a junction temperature range t j ?40 to +150 c storage temperature range t stg ?55 to +150 c 9. thermal resistance all values refer to gnd pins parameters symbol value unit junction - pin, measured to gnd, pins 6 to 9 and 20 to 23 r thjp 25 k/w junction ambient r thja 65 k/w 10. operating range all values refer to gnd pins parameters pins symbol min. typ. max. unit supply voltage 5, 10 v vs v uv (1) 40 (2) v logic supply voltage 19 v vcc 4.5 5 5.5 v logic input voltage 17, 24 to 26 v inh , v di , v clk , v cs ?0.3 v vcc v serial interface clock frequency 25 f clk 2mhz junction temperature t j ?40 +150 c notes: 1. threshold for undervoltage detection 2. output disabled for v vs > v ov (threshold for overvoltage detection)
8 4545d?bcd?04/09 u6815bm 11. noise and surge immunity parameters test conditions value conducted interferences iso 7637-1 level 4 (1) interference suppression vde 0879 part 2 level 5 esd (human body model) mil-std-883d method 3015.7 2 kv esd (machine model) eos/esd - s 5.2 150v note: 1. test pulse 5: v smax = 40v 12. electrical characteristics 7.5v < v vs < 40v; 4.5v < v vcc < 5.5v; inh = high; ?40c < tj < 150c; unless ot herwise specified, all values refer to gnd pins. parameters test conditions/pins symbol min. typ. max. unit current consumption quiescent current (v s ) v vs < 16v, inh or bit si = low pins 5, 10 i vs 40 a quiescent current (v cc ) 4.5v < v vcc < 5.5v, inh or bit si = low, pin 19 i vcc 20 a supply current (v s ) normal operating v vs < 16v, pins 5, 10 all output stages off i vs 0.8 1.2 ma all output stages on, no load i vs 10 ma supply current (v cc ) 4.5v < v vcc < 5.5v, normal operating, pin 19 i vcc 150 a internal oscillator frequency frequency (time-base for delay timers) f osc 19 45 khz over- and undervoltage detection, power-on reset power-on reset threshold pin 19 v vcc 3.4 3.9 4.4 v power-on reset delay time after switching on v vcc t dpor 30 95 160 s undervoltage detection threshold pins 5, 10 v uv 5.5 7.0 v undervoltage detection hysteresis pins 5, 10 v uv 0.4 v undervoltage detection delay t duv 721ms overvoltage detection threshold pins 5, 10 v ov 18 22.5 v overvoltage detection hysteresis pins 5, 10 v ov 1v overvoltage detection delay input register, bit 14 (sct) = high t dov 721ms overvoltage detection delay input register, bit 14 (sct) = low t dov 1.75 5.25 ms thermal prewarning and shutdown thermal prewarning, set t jpwset 125 145 165 c thermal prewarning, reset t jpwreset 105 125 145 c thermal prewarning hysteresis t jpw 20 k thermal shutdown, off t j switch off 150 170 190 c thermal shutdown, on t j switch on 130 150 170 c thermal shutdown hysteresis t j switch off 20 k notes: 1. only valid for version u6815bm-n. 2. delay time between rising edge of cs after data transmissi on and switch-on output stages to 90% of final level.
9 4545d?bcd?04/09 u6815bm ratio thermal shutdown, off/thermal prewarning, set t j switch off/ t jpw set 1.05 1.17 ratio thermal shutdown, on/thermal prewarning, reset t j switch on/ t jpw reset 1.05 1.2 output specification (ls1 to ls6, hs1 to hs6), 7.5v < v vs < v ov on resistance, low i out = 600 ma, pins 1, 4, 11, 14, 16 and 27 r ds on l 1.5 on resistance, high i out = ?600 ma, pins 2, 3, 12, 13, 15 and 28 r ds on h 2.0 output clamping voltage i ls1?6 = 50 ma, pins 1, 4, 11, 14, 16, 27 v ls1?6 40 60 v output leakage current v ls1?6 = 40v, all output stages off, pins 1, 4, 11, 14, 16 and 27 i ls1?6 10 a v hs1?6 = 0v, all output stages off, pins 2, 3, 12, 13, 15 and 28 i hs1?6 ?10 a inductive shutdown energy (1) pins 1-4, 11-16, 27 and 28 w outx 15 mj output voltage edge steepness pins 1-4, 11-16, 27 and 28 dv ls1?6 /dt dv hs1?6 /dt 50 200 400 mv/ s overcurrent limitat ion and shutdown threshold pins 1, 4, 11, 14, 16 and 27 i ls1?6 650 950 1250 ma pins 2, 3, 12, 13,15 and 28 i hs1?6 ?1250 ?950 ?650 ma overcurrent shutdown delay time input register, bit 14 (sct) = high t dsd 70 100 140 ms input register, bit 14 (sct) = low t dsd 8.75 17.5 ms open-load detection current input register, bit 13 (old) = low, output off, pins 1, 4, 11, 14, 16, 27 i ls1?6 60 200 a input register, bit 13 (old) = low, output off, pins 2, 3, 12, 13, 15, 28 i hs1?6 ?150 ?30 a open-load detection current ratio i ls1?6/ i hs1?6 1.2 open-load detection threshold input register, bit 13 (old) = low, output off, pins 1, 4, 11, 14, 16, 27 v ls1?6 0.6 4 v input register, bit 13 (old) = low, output off, pins 2, 3, 12, 13, 15, 28 v vs? v hs1?6 0.6 4 v output switch on delay (2) r load = 1 k t don 0.5 ms r load = 1 k t doff 1ms inhibit input input voltage low level threshold pin 17 v il 0.3 v vcc v input voltage high level threshold pin 17 v ih 0.7 v vcc v hysteresis of input voltage pin 17 v i 100 700 mv pull-down current v inh = v vcc, pin 17 i pd 10 80 a 12. electrical characteristics (continued) 7.5v < v vs < 40v; 4.5v < v vcc < 5.5v; inh = high; ?40c < tj < 150c; unless ot herwise specified, all values refer to gnd pins. parameters test conditions/pins symbol min. typ. max. unit notes: 1. only valid for version u6815bm-n. 2. delay time between rising edge of cs after data transmissi on and switch-on output stages to 90% of final level.
10 4545d?bcd?04/09 u6815bm serial interface - logic inputs (di, clk, cs) input voltage low level threshold pins 24 to 26 v il 0.3 v vcc v input voltage high level threshold pins 24 to 26 v ih 0.7 v vcc v hysteresis of input voltage pins 24 to 26 v i 50 500 mv pull-down current, pins di and clk v di , v clk = v vcc, pins 25, 26 i pdsi 250a pull-up current pin cs v cs = 0v, pin 24 i pusi ?50 ?2 a serial interface - logic output (do) output voltage low level i ol = 3 ma, pin 18 v dol 0.5 v output voltage high level i ol = ?2 ma, pin 18 v doh v vcc ? 1v v leakage current (tristate) v cs = v vcc, 0v < v do < v vcc, pin 18 i do ?10 10 ma 12. electrical characteristics (continued) 7.5v < v vs < 40v; 4.5v < v vcc < 5.5v; inh = high; ?40c < tj < 150c; unless ot herwise specified, all values refer to gnd pins. parameters test conditions/pins symbol min. typ. max. unit notes: 1. only valid for version u6815bm-n. 2. delay time between rising edge of cs after data transmissi on and switch-on output stages to 90% of final level. 13. serial interface ? timing parameters test conditions timing chart no. (1) symbol min. typ. max. unit do enable after cs falling edge c do = 100 pf 1 t endo 200 ns do disable after cs rising edge c do = 100 pf 2 t disdo 200 ns do fall time c do = 100 pf ? t dof 100 ns do rise time c do = 100 pf ? t dor 100 ns do valid time c do = 100 pf 10 t doval 200 ns cs setup time 4 t cssethl 225 ns cs setup time v do < 0.2 v vcc 8t cssetlh 225 ns cs high time input register, bit 14 (sct) = high 9t csh 140 ns input register, bit 14 (sct) = low 9t csh 17.5 ns clk high time 5 t clkh 225 ns clk low time 6 t clkl 225 ns clk period time ? t clkp 500 ns clk setup time 7 t clksethl 225 ns clk setup time 3 t clksetlh 225 ns di setup time 11 t diset 40 ns di hold time 12 t dihold 40 ns note: 1. see figure 13-1 on page 11
11 4545d?bcd?04/09 u6815bm figure 13-1. serial interface timing diagram with chart numbers for chart numbers, see table ?serial interface ? timing? on page 10 . do clk di clk clk c s 1 4 7 5 3 8 6 11 10 12 9 2 do o u tp u t do: high level = 0. 8 v cc , low level = 0.2 v cc inp u t s di, clk, c s : high level = 0.7 v cc , low level = 0. 3 v cc
12 4545d?bcd?04/09 u6815bm figure 13-2. application circuit 14. application notes it is strongly recommended to connect the blocking capacitors at v cc and v s as close as possi- ble to the power supply and gnd pins. recommended value for capacitors at v s : electrolythic capacitor c > 22 f in parallel with a ceramic capacitor c = 100 nf. value for elec- trolytic capacitor depends on ex ternal loads, conducted interfer ences, and reverse conducting current i hsx (see table absolute maximum ratings). recommended value for capacitors at v cc : electrolythic capacitor c > 10 f in parallel with a ceramic capacitor c = 10 0 nf. to reduce ther- mal resistance, it is recommended to place cooli ng areas on the pcb as close as possible to the gnd pins. do inh power on re s et control logic f au lt detector s i h s 5 l s 5 h s 4 l s 4 h s 6 l s 6 h s 2 l s 2 h s 1 l s 1 input re g i s ter ouput re g i s ter h s 3 ov - protection v s l s 3 s r r o l d h s 1 l s 1 h s 2 l s 2 h s 3 l s 3 h s 4 l s 4 h s 5 l s 5 h s 6 l s 6 p s f t p i n h s c d s c t re s et trigger micro- controller u5021m w a tchdog v s v cc v cc v cc v s v s 1 3 v v b a tt f au lt detector f au lt detector f au lt detector f au lt detector f au lt detector f au lt detector f au lt detector f au lt detector vcc v s 15 26 en ab le 25 di clk c s 1 8 17 24 1 3 12 3 22 8 16 14 11 4 1 27 10 5 h s 1h s 2h s3 h s 4h s 5h s 6 l s 1l s 2l s3 l s 4l s 5l s 6 byt41d v s v s gnd gnd gnd gnd gnd gnd gnd gnd vcc f au lt detector o s c uv - protection therm a l protection f au lt detector f au lt detector 5v v cc 6 7 8 9 20 21 22 2 3 19 + + m m m
13 4545d?bcd?04/09 u6815bm 16. package information 17. revision history 15. ordering information extended type number package remarks u6815bm-nfly so28 tubed, pb-free U6815BM-NFLG3Y so28 taped and reeled, pb-free technical drawings according to din specifications 0.25 0.10 package so28 dimensions in mm 0.4 1.27 16.51 18.05 17.80 2.35 7.5 7.3 9.15 8.65 10.50 10.20 0.25 28 15 114 please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4545d-bcd-04/09 ? put datasheet in a new template ? absolute maximum ratings table changed 4545c-bcd-09/05 ? put datasheet in a new template ? pb-free logo on page 1 added ? new heading rows on table ?absolute maximum ratings? on page 7 added ? table ?ordering information? on page 13 changed
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